8:00–9:00
Atrium

Registration / Coffee and Breakfast

9:00–10:00
Big Tex Auditorium

KEYNOTE ADDRESS

TECHNOLOGY AND MARKETS:
A Vision for Growth

Ken Hansen
Senior Fellow, Vice President and
Chief Technology Officer
              Freescale Semiconductor

10:15-10:40

Energy-Delay Space Exploration of Clocked Storage Elements Using Circuit Sizing
Mustafa Aktan, Sivakumar Paramesvaran, Joosik Moon, Vojin Oklobdzija

A 45nm Testchip Featuring Fast14 Domino Logic
Michael Seningen, Greg Roberts, Terri Pascoe

10:40-11:05

Physical Synthesis: the Good, the Bad, and the Ugly
Charles Alpert

Implementing Digital Logic with Sinusoidal Supplies
Kalyana Bollapalli, Sunil Khatri, Laszlo Kish

11:05-11:30

A Weighted Partial MaxSAT Based Method to Determine the MLV for Combinational Designs
Singh Amrinder, Kanupriya Gulati, Sunil Khatri

Per-Element-based Memory Supplies and Reconfiguration Schemes
Rouwaida Kanj, Rajiv Joshi, Zhuo Li, JB Kuang, Nancy Zhou, Weiping Shi, Sani Nassif

11:30–11:55

Dynamic Power Analysis for Custom Designs
Stephen Bijansky, Bassam Mohd, Baker Mohammad

Improved SRAM Design using Adaptive Architectures
Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky

12:00–1:30
Atrium

Lunch

1:00-2:00
(with authors)
2:00-5:00
(open viewing)
Atrium

Posters

List of posters

2:00-3:30
Big Tex Auditorium

Embedded Tutorial:
Coming Soon! VLSI in 3D...
(Design and Methodology Considerations of 3D Integration)

Gary Carpenter
IBM Austin Research Laboratory

Track 3:
CAD-2
Big Tex Auditorium
Session Chair:
Michael Orshansky

Track 4:
ANALOG-1
Li'l Tex Auditorium
Session Chair:
Axel Thomsen

3:45-4:10

Leakage Minimization with Reduced Mask Cost using Electrically-Driven Optical Proximity Correction
Shayak Banerjee, Praveen Elakkumanan, James Culp, Michael Orshansky

A High Resolution Low Voltage Rail-to-Rail Comparator Based on Floating and Quasi-Floating Gate Techniques
Jaime Ramirez-Angulo, Javier Hernandez-Alvidrez

4:10-4:35

Machine Learning Classification for Process Hotspot Detection with Edge-based Critical Signature Extraction
Duo Ding, David Pan

Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications
Kevin Smith

4:35-5:00

Design and Technology Co-Development of Design Rules for Advanced Technology Scaling
Jingrong Zhou, Indradeep Sen, Drew Carlson, Greg Northrop

RF Front End Design for 4G Wireless System Receiver
Kinchit Desai, Mehrdad Nourani, Sayed Askari, Bhaskar Banerjee

5:00–7:00
Atrium

Reception

9:00-10:00
Atrium

Registration / Coffee and Pastries

Track 5:
ARCHITECTURE
Big Tex Auditorium
Session Chair:
Derek Chiou

Track 6:
ANALOG-2
Li'l Tex Auditorium
Session Chair:
Axel Thomsen

10:15-10:40

Synthesis of Higher-Order K-Delta-1-Sigma Modulators for Wideband Analog to Digital Conversion
Vishal Saxena, R. Jacob Baker

10:40-11:05

CMOS Image Sensor using Delta-Sigma Modulation
Dennis Montierth, Kuangming Yap, R. Jacob Baker

11:05-11:30

A 22mW 227Msps 11b Self-Tuning ADC based on Time-to-Digital Conversion
Huihua Huang, Carl Sechen

11:30–11:55

Full Feed-Forward K-Delta-1-Sigma Modulator
Kaijun Li, Vishal Saxena, Geng Zheng, R. Jacob Baker

12-1:00
Atrium

Lunch

1:00-2:00
Big Tex Auditorium

KEYNOTE ADDRESS

Lighting up Dark Silicon

Krisztián Flautner
Vice President of Research and Development
ARM Ltd

Track 7:
CAD-3
Big Tex Auditorium
Session Chair:
Vojin G. Oklobdzija

Track 8:
PROCESS TECHNOLOGY
Li'l Tex Auditorium
Session Chair:
Michael Seningen

2:10–2:35

A Linear Complexity Incremental Defect Mapping Method for Reconfigurable Computing Platforms in the Presence of Prevalent Defects
Bao Liu

Design-Transparent Alternative Resistor and E-fuse for a Metal-Gate High-k CMOS PDSOI Technology
Kaveri Mathur, James Buller, Andreas Kurz, Christoph Schwan, Kerstin Ruttloff, Andy Wei

2:35-3:00

Power Efficient Standard Cell Library Design
Ryan Afonso, Hiran Tennakoon, Carl Sechen

Optimization of Stress Liner Interface Location to Improve Circuit-level Performance for Dual-Stress Liner (DSL) Device Architecture
Akif Sultan, Sean Hannon, Kailash Agrawal, Michael Austin, John Faricelli, Sushant Suryagandh, Ed Ehrichs, Scott Goad, Rob Dupcak, Darin Chan, James Buller, Larry Bair, Ali Icel, David Wu, Ralf Richter, Hartmut Ruelke, Volker Grimm, Fernando Koch, Carsten Reichel, Edmund Weissbeck, Kerstin Ruttloff, Stephan-Detlef Kronholz, Thorsten Kammler, Karsten Wieczorek

3:00-3:25

Hardware Design Methodology from TLM 2.0 to RTL
Nadereh Hatami, Paolo Prinetto, Antonio Trapanese

Improved Charge-Based Capacitance Measurement for Advanced IC Technology
Jianhong Zhu, Tilo Mantei, James Buller

3:25-3:50

A Constrained Discrete Dynamic Optimization Method for Concurrent Repeater Insertion and Gate Sizing in Multi-Core Design
Salim Chowdhury

A New NBTI Sensor for Chip Multi-Processor (CMP) Monitoring Applications
Patrick Green, Janet Wang-Rovenda

3:50-4:00
Atrium

Break

Embedded Tutorial:
Big Tex Auditorium

Embedded Tutorial:
Li'l Tex Auditorium

4:00-5:30

Silicon-based Millimeter-Wave Multiple-Antenna Transceivers: From Beamforming to Baseband

Harish Krishnaswamy

Designing Multi-Processor and Multi-Core Systems-on-Chip


Andreas Gerstlauer