PUBLICITY CHAIR: Stephanie Peco, Univ. of Texas - Austin
PROGRAM COMMITTEE: Magdy Abadir, Freescale Willie Anderson,
Qualcomm Fares Bagh, Advent Solar Ramyanshu (Romi) Datta Texas Instruments Anirudh Devgan, Magma Kevin Nowka, IBM Vojin Oklobdzija Univ. of Texas - Dallas John Paulos, Consultant Ramin Poorfard, Silicon Labs Nur Touba, Univ. of Texas - Austin Mike Warner,
Mentor Graphics Ron Waters, TSMC
4th Annual
Austin Conference on
Integrated Systems & Circuits 2009
Oct 26-27 , 2009
Mon-Tues The Commons Center
J.J. Pickle Center, Austin Texas
Track 4:
ANALOG-1
Li'l Tex Auditorium Session Chair: Axel Thomsen
3:45-4:10
Leakage Minimization with Reduced Mask Cost using Electrically-Driven Optical Proximity Correction Shayak Banerjee, Praveen Elakkumanan, James Culp, Michael Orshansky
A High Resolution Low Voltage Rail-to-Rail Comparator Based on Floating and Quasi-Floating Gate Techniques Jaime Ramirez-Angulo, Javier Hernandez-Alvidrez
4:10-4:35
Machine Learning Classification for Process Hotspot Detection with Edge-based Critical Signature Extraction Duo Ding, David Pan
Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications Kevin Smith
4:35-5:00
Design and Technology Co-Development of Design Rules for Advanced Technology Scaling Jingrong Zhou, Indradeep Sen, Drew Carlson, Greg Northrop
RF Front End Design for 4G Wireless System Receiver Kinchit Desai, Mehrdad Nourani, Sayed Askari, Bhaskar Banerjee
5:00–7:00
Atrium
Reception
Tuesday
Oct 27, 2009
9:00-10:00
Atrium
Registration / Coffee and Pastries
Track 5: ARCHITECTURE Big Tex Auditorium Session Chair: Derek Chiou
Track 6: ANALOG-2
Li'l Tex Auditorium Session Chair: Axel Thomsen
Track 7:
CAD-3 Big Tex Auditorium
Session Chair: Vojin G. Oklobdzija
Track 8:
PROCESS TECHNOLOGY
Li'l Tex Auditorium
Session Chair: Michael Seningen
2:10–2:35
A Linear Complexity Incremental Defect Mapping Method for Reconfigurable Computing Platforms in the Presence of Prevalent Defects Bao Liu
Design-Transparent Alternative Resistor and E-fuse for a Metal-Gate High-k CMOS PDSOI Technology Kaveri Mathur, James Buller, Andreas Kurz, Christoph Schwan, Kerstin Ruttloff, Andy Wei
2:35-3:00
Power Efficient Standard Cell Library Design
Ryan Afonso, Hiran Tennakoon, Carl Sechen
Optimization of Stress Liner Interface Location to Improve Circuit-level Performance for Dual-Stress Liner (DSL) Device Architecture Akif Sultan, Sean Hannon, Kailash Agrawal, Michael Austin, John Faricelli, Sushant Suryagandh, Ed Ehrichs, Scott Goad, Rob Dupcak, Darin Chan, James Buller, Larry Bair, Ali Icel, David Wu, Ralf Richter, Hartmut Ruelke, Volker Grimm, Fernando Koch, Carsten Reichel, Edmund Weissbeck, Kerstin Ruttloff, Stephan-Detlef Kronholz, Thorsten Kammler, Karsten Wieczorek
3:00-3:25
Hardware Design Methodology from TLM 2.0 to RTL
Nadereh Hatami, Paolo Prinetto, Antonio Trapanese
Improved Charge-Based Capacitance Measurement for Advanced IC Technology Jianhong Zhu, Tilo Mantei, James Buller
3:25-3:50
A Constrained Discrete Dynamic Optimization Method for Concurrent Repeater Insertion and Gate Sizing in Multi-Core Design Salim Chowdhury
A New NBTI Sensor for Chip Multi-Processor (CMP) Monitoring Applications Patrick Green, Janet Wang-Rovenda