8:00–9:00
Atrium

Registration / Coffee and Breakfast Tacos

9:00–10:00
Big Tex Auditorium

KEYNOTE ADDRESS

Dr. Necip Sayiner,
President, CEO, and Board Member
Silicon Laboratories

10:30-10:55

Design Automation and Verification Methodology Challenges of the Intel Atom Processor
Rajesh Gupta

Invited Paper:
Biosensor Microarrays in CMOS
Arjang Hassibi

10:55–11:20

Reducing Flip-Flop Power for DSP Design
Bassam Mohd, Martin Saint-Laurent, Paul Bassett, and Shahid Imam

Rail to Rail Fully Differential Sample and Hold Based on Clocked Diffrential Difference Amplifier using Resistive Local Common Mode Feedback
Jaime Ramirez-Angulo, Clara Lujan-Martinez, Carlos Rubia-Marcos, Ramon G. Carvajal, and Antonio Lopez-Martin

11:20–11:45

Adaptive Voltage Tuning for Dual-Vdd ASICs
Stephen Bijansky and Adnan Aziz

Buck-Boost Converter Based Power Conditioning Circuit for Low Excitation Vibrational Energy Harvesting
Arvindh Rajasekaran, Abhiman Hande, and Dinesh Bhatia

11:45–1:20
Atrium

Lunch

Track 3:
CAD-1
Big Tex Auditorium
Session Chair:
Michael Solka

Track 4:
COMPUTER ARITHMETIC
Li'l Tex Auditorium
Session Chair:
Earl Swartzlander

1:20–1:45

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Bin Zhang and Michael Orshansky

Invited Paper:
Automated Multiplier Design
K'Andrea C. Bickerstaff and Earl Swartzlander

1:45–2:10

ELIAD: Efficient Lithography Aware Detailed Router with Compact Post-OPC Printability Prediction
Minsik Cho, Kun Yuan, Yongchan Ban, and David Z. Pan

Full Adder Evaluation and Selection for a Parallel Multiplier
Mike Spear, Gaurav Tuteja, and Earl Swartzlander

2:10–2:35

COOLER - A Fast Multiobjective Fixed-Outline Thermal Floorplanner
Debarshi Chatterjee, Theodore Manikas, and Igor Markov

Dual Vdd Design Optimization of Fast Multipliers
Eun Jung Jang, Earl Swartzlander, and Jebediah Keefe

2:35–3:00

Dynamic Compaction with Recursive Learning for Delay Test
Zheng Wang and Duncan M. H. Walker

A Hybrid Approach to Last Stage Addition for Wallace and Dadda Multipliers
James Haydn Nelson, Eiman Ebrahimi, Mahnaz Sadoughi, and Earl Swartzlander

3:00-3:30
Atrium

Break

3:30–5:00
Big Tex Auditorium

Embedded Tutorial:
Fractional-N PLL
Dr. Axel Thomsen,
Silicon Labs

5:00–6:30
Atrium

Reception / Dinner

8:00–9:00
Atrium

Registration / Coffee and Pastries

9:00-10:00
Big Tex Auditorium

KEYNOTE ADDRESS

Dr. Jason Rhode,
President and CEO
Cirrus Logic

Track 5:
DIGITAL DESIGN-2
Big Tex Auditorium
Session Chair:
Adnan Aziz

Track 6:
ANALOG AND RF
Li'l Tex Auditorium
Session Chair:
TR Viswanathan

10:15-10:40

Invited Paper:
Receivers Design: Case Studies
Hesam Amir-Aslanzadeh and Edgar Sanchez-Sinencio

10:40–11:05

Feed-Forward Interference Suppression for Broadband Systems
Xin Wang and Ranjit Gharpurey

11:05–11:30

A Linear Transconductor using Series-Connected CMOS Quad
Venkatesh Acharya, Bhaskar Banerjee, and TR Viswanathan

11:30–11:55

Indirect Compensation Techniques for Three-Stage CMOS Op-Amps
Vishal Saxena, Jacob Baker, and TR Viswanathan

11:55-1:20
Atrium

Lunch

Track 7:
CAD-2
Big Tex Auditorium
Session Chair:
Michael Orshansky

Track 8:
SYSTEMS & ARCHITECTURES
Li'l Tex Auditorium
Session Chair:
Mattan Erez

1:20–1:45

3D Resistance Extraction with Lithographic and Scattering Effect
Ying Zhou, Zhuo Li, and Weiping Shi

Power Analysis of a Path-Based Perception Branch Predictor
Justin Friesenhahn, Lizy Kurian John, and Mark McDermott

1:45–2:10

Accelerating Statistical Static Timing Analysis using Graphics Processing Units
Kanupriya Gulati and Sunil Khatri

Hardware / Software Tradeoffs in Multicore Architectures
Steven Guccione

2:10–2:35

Autonomous Optical Proximity Correction: The New Frontier of Design for Manufacturing?
Shanhu Shen, Peng Yu, and David Z. Pan

Workload Slicing for Detailed Pre-Silicon Power Estimation
Hassan Al-Sukhni, James Holt, David Lindberg, and Michele Reese

2:35-3:00
Atrium

Break

3:00-4:30
Big Tex Auditorium

Embedded Tutorial:
Holistic Coupling of Manufacturing and Design
Dr. Sani Nassif,
IBM

4:30-6:00
Atrium

Poster Session / Reception

6:00-9:00
The Domain, Building 5

Brain Party II
DOS TECHIES
sponsored by the Austin Chamber of Commerce

8:40–10:10
Li'l Tex Auditorium

TUTORIAL
Out of Order Superscalar Architecture
Dr. Derek Chiou,
University of Texas at Austin

10:10-10:30
Atrium

Break

10:30–12:0
Li'l Tex Auditorium

TUTORIAL
Constraint Solving for Functional Verification
Dr. Andreas Kuhlmann,
Cadence Berkeley Labs